Serdes
Advanced serial IO in scaled CMOS processes.
Our design experience in SerDes encompasses a wide array of applications and technologies:
- 17-20Gb/s Backplane PHY: 4 lanes, 40nm-28nm, long reach very lossy channels
- 4-10Gb/s Chip to Chip interconnect, 90nm-40nm, short reach optimized for very low power dissipation
- 10Gb/s Ethernet PHY for fiber optics, 130nm-40nm, including XFI and EDC for LRM
- 5.4Gb/s CPU to GPU: 20 lanes, 65nm, custom interface with clock forwarding
- 2.5-3.125Gb/s: PCIE, SATA, XAUI, MIPI, 130nm-45nm
Our breakthrough technology and IP achieves best in class power dissipation and overcomes losses and reflections in extremely hostile channels.